A High Performance Unified BCD and Binary Adder/Subtractor

Abstract

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.