ALPS: an algorithm for pipeline data path synthesis

Abstract

While techniques for design of high performance computing systems have been well understood, software mechanisms for the automatic design of high performance application specific integrated circuits (ASICS) remain relatively u nexplored. Advances in levels of integration will make it feasible to support performance-enhancing structures on a single chip. With the increasing demand for high performance in real-time signal processing applications, the design of high speed ASICS merits immediate attention. In this paper, we develop software mechanisms for the high-level synthesis of high-performance VLSI systems. We have extended our interactive behavioral synthesis framework that provides scheduling with multiple constraints including performance and cost, to support scheduling for high-performance. The system is powerful enough to allow trade-offs along mnltiple dimensions. The software mechanisms to support highperformance include a pipeline scheduler, ALPS, that suppol ts constraints including performance and cost. ALPS is a polynomial time algorithm. Experimental results have shown that (a) ALPS consistently synthesizes designs on the optimal-designs curve, (b) it can be used for rapid prototypiug as well as for detailed synthesis, and (c) the interplay between performance and cost results in a rich set of design alternatives.