{"title":"Optimal design and coulomb blockade suppressed leakage of carbon nanotube transistors","authors":"K. Alam, R. Lake","doi":"10.1109/DRC.2005.1553106","DOIUrl":null,"url":null,"abstract":"We consider a 1.5 nm diameter (19,0) CNT for which zero-Schottky-barrier contacts have been demonstrated. The model device has a wrap-around gate, 2 nm ZrO2 dielectric, and the Fermi level of the metal contacts aligned with the conduction band of the source and drain. A number of different CNT lengths with various source/drain asymmetry are studied. A 40 nm length CNT with a 10 nm gate shows excellent performance as quantified below. We numerically calculate the gate delay (taus = C9VDD/ION), ON/OFF current ratio, and inverse subthreshold slope as a function of source to gate underlap L exS","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"9 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. DRC '05.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2005.1553106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We consider a 1.5 nm diameter (19,0) CNT for which zero-Schottky-barrier contacts have been demonstrated. The model device has a wrap-around gate, 2 nm ZrO2 dielectric, and the Fermi level of the metal contacts aligned with the conduction band of the source and drain. A number of different CNT lengths with various source/drain asymmetry are studied. A 40 nm length CNT with a 10 nm gate shows excellent performance as quantified below. We numerically calculate the gate delay (taus = C9VDD/ION), ON/OFF current ratio, and inverse subthreshold slope as a function of source to gate underlap L exS