Optimal design and coulomb blockade suppressed leakage of carbon nanotube transistors

K. Alam, R. Lake
{"title":"Optimal design and coulomb blockade suppressed leakage of carbon nanotube transistors","authors":"K. Alam, R. Lake","doi":"10.1109/DRC.2005.1553106","DOIUrl":null,"url":null,"abstract":"We consider a 1.5 nm diameter (19,0) CNT for which zero-Schottky-barrier contacts have been demonstrated. The model device has a wrap-around gate, 2 nm ZrO2 dielectric, and the Fermi level of the metal contacts aligned with the conduction band of the source and drain. A number of different CNT lengths with various source/drain asymmetry are studied. A 40 nm length CNT with a 10 nm gate shows excellent performance as quantified below. We numerically calculate the gate delay (taus = C9VDD/ION), ON/OFF current ratio, and inverse subthreshold slope as a function of source to gate underlap L exS","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. DRC '05.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2005.1553106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

We consider a 1.5 nm diameter (19,0) CNT for which zero-Schottky-barrier contacts have been demonstrated. The model device has a wrap-around gate, 2 nm ZrO2 dielectric, and the Fermi level of the metal contacts aligned with the conduction band of the source and drain. A number of different CNT lengths with various source/drain asymmetry are studied. A 40 nm length CNT with a 10 nm gate shows excellent performance as quantified below. We numerically calculate the gate delay (taus = C9VDD/ION), ON/OFF current ratio, and inverse subthreshold slope as a function of source to gate underlap L exS
碳纳米管晶体管的优化设计和库仑阻塞抑制泄漏
我们考虑一个直径为1.5 nm(19,0)的碳纳米管,其零肖特基势垒接触已被证明。该模型器件具有环绕栅极,2 nm ZrO2介电介质,金属触点的费米电平与源极和漏极的导带对齐。研究了具有不同源漏不对称性的碳纳米管长度。40nm长度的碳纳米管和10nm栅极显示出优异的性能,如下图所示。我们数值计算了栅极延迟(taus = C9VDD/ION)、开/关电流比和逆亚阈值斜率作为源与栅极重叠lexs的函数
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