Efficient 8-cycle DES implementation

Abstract

This paper describes an efficient DES implementation that encrypts a 64-bit plain text block in 8 clock cycles. The 8 cycle processing latency optimizes the throughput of a pipelined DES system, where a byte-wide bus is used. Also, by decreasing the system clock frequency by a factor of 2, the switching power consumption is reduced compared to the conventional implementations. Our approach is based on the time multiplexed cipher function that requires only one copy of S-Box realization unlike other 8-cycle implementations.