Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology

Abstract

We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction for the micro controller unit (MCU) compared to the conventional low power (LP) process. Measurement result also shows the DDC process improves 56.5 % and 15.0 % of operating frequency, 200 mV and 50 mV of supply voltage margin, or 23.8 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively, even if the Vth of the LP process is adjusted to that of the DDC process. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.