Frequency dividers with enhanced locking range

Abstract

The locking range of the CML divide-by-two divider with the inductive shunt peaking is analyzed. The dividers using the locking-range-enhanced techniques have been realized in 0.13 mum CMOS process. Experimental results show that the locking range of the proposed divider is improved 30.8% and 62.5% by adopting the current-reused and the gm-boosted technique, respectively. When both techniques are adopted, the locking range is 101.67% larger than the conventional one at the same power consumption. The maximum locking range of the proposed divider is from 46.22 to 48.64 GHz while the input power level is -4 dbm.