Scaling issues of n-channel vertical tunnel FET with /spl delta/p/sup +/ SiGe layer

K. Bhuwalka, J. Schulze, I. Eisele
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引用次数: 6

Abstract

The performance of a n-channel vertical tunnel field-effect transistor is shown to improve significantly by bandgap engineering at the tunneling junction. The bandgap modulation is achieved by inserting a heavily doped 3 nm delta SiGe layer at the p-source end. Since the bandgap at the tunneling junction determines the tunneling barrier height, having a SiGe delta layer results in lowering it. Thereby, increasing the tunneling probability under similar bias conditions. We show that controlling the Ge mole fraction, x, in SiGe, gives an additional parameter for control of device performance. Device on-current, I/sub on/, and threshold voltage, V/sub T/, are seen to improve considerably. However, as the device is scaled down, the tunneling probability increases significantly even for V/sub GS/=0 V as x is increased. Thereby, leading to large increase in tunneling leakage current. Optimization of the device performance can then be done by appropriate choice of x with gate oxide thickness, t/sub ox/, according to technology requirements.
具有/spl delta/p/sup +/ SiGe层的n沟道垂直隧道场效应管的缩放问题
通过隧道结带隙工程,n沟道垂直隧道场效应晶体管的性能得到了显著提高。带隙调制是通过在p源端插入一个重掺杂的3nm δ SiGe层来实现的。由于隧道结处的带隙决定了隧道势垒的高度,因此SiGe δ层的存在会降低势垒的高度。从而增加了相似偏压条件下的隧穿概率。我们表明,在SiGe中控制Ge摩尔分数x,为控制器件性能提供了一个额外的参数。器件通流(I/sub on/)和阈值电压(V/sub T/)明显改善。然而,随着器件的缩小,即使在V/sub GS/=0 V下,隧穿概率也随着x的增加而显著增加。从而导致隧道漏电流的大幅度增加。然后可以根据技术要求,通过适当选择x与栅氧化层厚度t/sub ox/来优化器件性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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