Guided-probe diagnosis of macro-cell-designed LSI circuits

Abstract

A novel guided-probe diagnostic method for macro cells has been developed. Since macro cells have no netlist corresponding to layout, CAD-navigation data and the logic-simulation netlist are derived from the macro-cell layout by extracting a transistor-level or leaf-cell-level netlist. A memory-macro cell, in which logic simulation was very difficult because of the cell's internal analog behavior has been converted into logically equivalent circuits for logic simulation. Here, analog-behavior leaf cells, such as sense amplifiers and pull-up transistors, were replaced with the corresponding logic-behavior models. The proposed method has been successfully applied to actual macro-cell-designed LSI data, and it has been verified that the logic models give a good timing resolution in the logic simulation. Using the proposed method, all kinds of macro-cell-designed LSIs will be able to be diagnosed, without the need for a "golden" device by an electron-beam guided probe.