A Low Loss Wideband DC-67 GHz SP3T Switching Network on 45nm SOI-CMOS Process

Abstract

In this paper, we present a wideband DC-67 GHz single-pole-triple-throw (SP3T) switch using a series-shunt topology on 45-nm silicon-on-insulator (SOI) CMOS process from global foundries. For wideband operation, series inductors are implemented to resonate out the parasitic capacitance at drain and source terminals of NMOS transistors used in the switch. Additionally, for shunt branches, a double stack-FET topology is used to handle higher power levels. In all, the switch has an insertion loss from 1.42 dB to 2.62 dB over frequency range from 10 MHz to 67 GHz. The measured input 1-dB compression power (IP1dB) at 20 GHz exceeds 10 dBm while the third order input intercept point (IIP3) at 20 GHz is 20.8 dBm.