Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology

Abstract

A methodology to optimally design multi-stage current-steering CMOS amplifiers is described. The optimal device operating conditions and sizes are directly calculated from design constraints, such as desired voltage gain, and frequency bandwidth. The proposed design algorithm is based on an analytical approach, which extends the conventional gm/ID lookup table methodology. Examples are provided to show effectiveness of the proposed approach.