128-GS/s ADC Front-End with Over 60-GHz Input Bandwidth in 22-nm Si/SiGe FDSOI CMOS

Abstract

The analog front-end of a 6-to-8 bit 128-GS/s SAR ADC architecture with record 60-GHz input bandwidth is presented. It includes the data path, 25% duty-cycle dc-32 GHz quadrature clock generator, 4 master, and 32 slave track-and-hold (T&H) circuits formed with CMOS series switches. Each of the 32 slave CMOS T&Hs drives either a $\pmb{50}-\Omega$ output buffer (for testing) or a 30-fF hold capacitor, representative of the load provided by each of the 32 SAR sub-ADCs. To achieve record bandwidth and sampling rate, the data distribution network and the single-ended-to-differential clock amplifier use novel 0.8-V n-MOS and 1.2-V p-MOS Cherry-Hooper buffers with good common-mode and supply rejection beyond 100 GHz, validated through small-and large-signal measurements. The 32-GHz quadrature clock generator is realized with a novel 80-GHz input bandwidth, 0.8- V quasi-CML static divider, followed by inductively-peaked CMOS logic circuits. The total power consumption of the analog frontend is 320 mW of which 120 mWare consumed by the data sampling interleaver and 200 mW bv the clock generation unit. It occupies a total die area of $\mathbf{0.65}\ \mathbf{mm}\times \mathbf{0.37}\ \mathbf{mm}$.