A 60 GHz multi-Gb/s system demonstrator utilizing analog synchronization and 1-bit data conversion

Abstract

In this paper, a 60 GHz system demonstrator for multi-Gb/s, short-range, line-of-sight communications is presented. The system utilizes a highly efficient receiver architecture with phase noise suppression capability, which performs carrier synchronization in the analog domain, eliminating the need for high speed, high precision analog-to-digital converters. In the presented demonstrator, with only 1-bit data conversion at the transmitter and receiver, an error-free maximum raw data rate of 3.45 Gb/s is achieved using BPSK modulation over a wireless transmission distance of up to 1m. A more sophisticated modulation capability is demonstrated as well for a raw data rate of 6.9 Gb/s and a bit error rate of 10-5 usina QPSK modulation.