Pilsoon Choi, Bugra Kanargi, K. Lee, C. Boon, E. Wang, C. S. Tan, D. Antoniadis, E. Fitzgerald
{"title":"Monolithically Integrated GaN+CMOS Logic Circuits Design and Electro-Thermal Analysis for High-Voltage Applications","authors":"Pilsoon Choi, Bugra Kanargi, K. Lee, C. Boon, E. Wang, C. S. Tan, D. Antoniadis, E. Fitzgerald","doi":"10.1109/BCICTS48439.2020.9392934","DOIUrl":null,"url":null,"abstract":"This paper presents a logic inverter circuit consisting of both CMOS and GaN devices to drive high-torque DC motors requiring high voltages in various robotics applications. The GaN+CMOS inverter can be monolithically integrated with CMOS digital circuits on a single die, accommodating a 5V CMOS logic level input and providing a 30V output voltage using depletion-mode GaN HEMTs without negative gate bias circuitry. Electro-thermal simulations are also performed to analyze the temperature of CMOS devices affected by nearby GaN HEMTs.","PeriodicalId":355401,"journal":{"name":"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS48439.2020.9392934","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a logic inverter circuit consisting of both CMOS and GaN devices to drive high-torque DC motors requiring high voltages in various robotics applications. The GaN+CMOS inverter can be monolithically integrated with CMOS digital circuits on a single die, accommodating a 5V CMOS logic level input and providing a 30V output voltage using depletion-mode GaN HEMTs without negative gate bias circuitry. Electro-thermal simulations are also performed to analyze the temperature of CMOS devices affected by nearby GaN HEMTs.