Modeling and optimization of TSV for crosstalk mitigation in 3D neuromorphic system

Abstract

Neuromorphic computing is an emerging technology that describes the biological neural systems and implementation of its electrical model in complementary metal-oxide-semiconductor (CMOS) VLSI system. Three dimensional (3D) integration can be applied in hardware implementation of neuromorphic computing that provides high device interconnection density using fast and energy efficient links with excellent distribution and communication among the neuron layers. In this work, we studied the necessities of neuromorphic computing based on 3D integration technology, design challenges, and a possible solution to overcome the effect of huge parallelism of well-connected synaptic system. Using the force directed optimization algorithm, an optimal interconnect array pattern is identified for a proposed structure that could mitigate significant amount of crosstalk. For the analysis of crosstalk, an electrical model of the optimal array structure is proposed and it has been validated by comparing its simulation results with those extracted from commercial tools. This work can be used as a basis study for successful implementation of next generation 3D neuromorphic computation for high performance application.