Parallel implementation of motion-compensation for HDTV video decoder

Abstract

A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder.