Design of Reversible Finite Field Arithmetic Circuits with Error Detection

J. Mathew, H. Rahaman, B. R. Jose, D. Pradhan
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引用次数: 6

Abstract

Motivated by the potential of reversible computing, we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2m). It is shown that an adder over GF(2m) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits. To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials. Our technique, when compared with existing CAD tool gives the same gate size and quantum cost.
具有误差检测的可逆有限域算术电路设计
在可逆计算潜力的激励下,我们提出了一种设计GF(2m)形式有限域或伽罗瓦域可逆算术电路的系统方法。结果表明,GF(2m)上的加法器可设计为m个垃圾位,PB乘法器可设计为2m个垃圾位。为了解决计算中的错误问题,我们还对电路进行了扩展,增加了错误检测功能。门数和面向技术的成本度量用于评估。对于特殊的原始多项式,导出了闸门尺寸上界的表达式。与现有的CAD工具相比,我们的技术具有相同的栅极尺寸和量子成本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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