CMOS Latch-Up Characterization using a Laser Scanner

Abstract

The technique of using a focused laser beam to induce latch-up in a CMOS circuit is introduced and described. The characterization method allows the quantitative assessment of a structure's latch-up margin and its dependence on operating parameters (supply voltage, temperature, etc). Various scans were performed on CMOS test structures with adjustable latch-up margins. CMOS latch-up parameters, such as the spreading resistance and the parasitic transistor betas, were found important in determining the sensitivity peaks (position of highest latch-up sensitivity to carrier generation). The shape and height of these peaks were found to be consistent with the commonly used two-transistor circuit.