Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application

Abstract

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100nm technology. In this paper, we present a highly stable 2-port 7T SRAM cell for ultra-low power in 90nm technology. The dynamic read noise margin is improved by 7X over conventional dual port SRAM. Finally, a 4Kb bit-interleaved SRAM architecture is presented using proposed cell. Experimental results show that memory consumes 1.26pJ/bit at 0.22V supply voltage with 2MHz performance. The dynamic read noise margin is improved by 7X over conventional dual port SRAM. The successful write and read operations can be performed at supply voltage as low as 0.17V. Two level write decoder architecture is used to eliminate the pseudo read problem in unselected columns.