Analyze of threshold voltage in SOI PMOSFET device using Taguchi method

2016 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2016-08-01 DOI:10.1109/SMELEC.2016.7573600

M. Aziz, F. Salehuddin, A. Zain, K. Kaharudin, H. Hazura, S. Idris, A. R. Hanim, Z. Manap

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引用次数: 1

Abstract

The short-channel effect (SCE) is the main problem of many metal-oxide-semiconductor field-effect transistor (MOSFET) industries. A lot of studies addressing the SCE effect have been conducted. One of the methods used for this is called SOI (silicon-on-insulator) technology. This method has been proven to effectively reduce the SCE effect. In this research paper, the electrical characteristic of an 18 nm gate length SOI PMOSFET was analyzed based on the prediction of the International Technology Roadmap for Semiconductors (ITRS). The threshold voltage would be the key characteristic in this research. Four process parameters were used with two noise factors in order to conduct nine sets of experiments using the L9 orthogonal array Taguchi method. At the end of the experiment, the best setting that was predicted by the Taguchi method would be utilized for the purpose of verification. The result shows that VTH after the optimization approach is closer to the nominal value (-0.533V), that is, within the appropriate range of ITRS 2013.

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用田口法分析SOI PMOSFET器件的阈值电压

短通道效应(SCE)是许多金属氧化物半导体场效应晶体管(MOSFET)行业面临的主要问题。人们对SCE效应进行了大量的研究。其中一种方法被称为SOI(绝缘体上硅)技术。该方法已被证明可以有效地降低SCE效应。本文基于国际半导体技术路线图(ITRS)的预测，分析了18 nm栅长SOI PMOSFET的电学特性。阈值电压将是本研究的关键特征。采用L9正交阵田口法，选取4个工艺参数加2个噪声因子，进行了9组实验。在实验结束时，将利用田口法预测的最佳设置进行验证。结果表明，优化方法后的VTH更接近标称值(-0.533V)，即在ITRS 2013的合适范围内。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE International Conference on Semiconductor Electronics (ICSE)

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