Excess loop delay compensation techniques in continuous-time ΔΣ modulators

Abstract

The circuit non-idealities such as the opamp nonidealities, the clock jitter, comparator offset, DAC mismatch and the excess loop delay degrade the performance of the Continuous-time Sigma Delta Modulator. A study of a methods used for excess loop delay compensation is presented in this paper. The model used to analyze the techniques is a third order Single-bit Modulator with the Specification of LTE Network. The model have a sampling frequency at 459 MHz within 10 MHz.