Dual Gate enhancement-mode JFET (DG-JFET) for ultra low power applications

Abstract

Dual Gate enhancement mode Junction Field Effect Transistors (DG-JFETs) was recognized as one of the possible choice to continue the scaling beyond the conventional limits. The need for ultra-low voltage ICs necessitates the scaling of MOSFETs beyond 25nm. However, the advanced standard MOSFET devices and CMOS technologies have several limitations for ultra-low voltage analog operation and the JFET devices offer a great potential for such applications. The device architecture and performance of 16nm enhancement mode SOI DG-JFET is analyzed in this work. DAVINCI (a synopsis 3D device simulation tool) is used to analyze the device architecture and performance initially. The numerical device simulation results show that the enhancement mode DG-JFETs offer low threshold voltage and an excellent ON/OFF performance at a power supply voltage of 0.5 V required for ultra-low voltage analog ICs.