Cost and Yield Analysis of Die-to-Wafer Hybrid Bonding

Abstract

Copper hybrid bonding has been a topic in microelectronics packaging for years now, as it enables connections that provide more bandwidth at lower power. Although wafer-to-wafer hybrid bonding has been in use in the CMOS industry since 2016, wafer-to-wafer bonding is limited to creating stacks where the top and bottom die are the same size. With die-to-wafer (D2W) hybrid bonding, heterogeneous integration of different-sized chips is enabled. However, questions remain about the cost of implementing this process, where precise placement of each chip is necessary for high yields. This paper discusses the D2W hybrid bonding process and explore the cost and yield in various scenarios.