Characteristics of short channel MOSFETs in the punch-through current mode

Abstract

Results of two-dimensional device analysis are compared with experiment for 0.8 µm Si-Gate ion implanted MOS devices operated under conditions of punch-through transport. Characterization of the punch-through mode of device operation (a critical factor which limits the maximum drain voltage of submicron MOS VLSI devices) with experiment and simulation has shown that the observed power law dependence of IDSvs VDS(VGS=VSB=0) is related to the drain induced barrier-height lowering. This simulation, which combines results of the process simulation program (SUPREM) and device simulation program (CADDET), is shown to predict the behavior of this mode of operation for sub-micron channel devices where previous one-dimensional theory has failed.