A novel process-variation insensitive network for on-chip impedance matching

Abstract

Impedance matching networks are used widely in RF circuit design for many purposes such as maximum power transfer or optimal noise match. Passive impedance matching networks involving capacitors and inductors are often employed, but they are subject to process variation. The paper presents a process-variation insensitive network with matched passive components that has a low sensitivity to process variation. This network,, when applied in impedance matching, can lead to a reliable network with high immunity to process variation. The improvement on immunity as compared to a conventional passive network is revealed in Monte Carlo simulation. This approach can be extended to broadband impedance matching by cascading the proposed network.