Dynamic hazards and speed independent delay model

Abstract

Different types of hazards have been studied extensively under the bounded gate and wire delay model. It is well known that under this delay model not all multiple input dynamic logic hazards can be removed from all two stage combinational logic circuits. In this paper we restrict the delay model to the well-known inertial gate delay or speed independent model and show that under this model half of the dynamic logic hazards can no longer occur in two level logic circuits. We then weaken the zero wire delay restriction and find an upper bound for the delay along critical interconnection wires and hence propose a virtual isochronic fork model for interconnection networks.