Using Verilog-to-Routing Framework for Coarse-Grained Reconfigurable Architecture Routing

Abstract

Coarse-Grained Reconfigurable Architectures gain popularity owing to their good energy efficiency and short reconfiguration times, crucial for dynamic reconfiguration. However, due to great diversity of architectures various approaches towards tooling has been adopted. As a result CGRAs lack common synthesis/compiling, placement and routing tools, available for well-developed and standardized FPGAs. This paper presents attempts to adapt and use open-source FPGA design framework Verilog-to-Routing for REuP architecture and a range of similarly constructed CGRAs.