Fault-Tolerant 3D-NoC Architecture and Design: Recent Advances and Challenges

Abstract

In this paper, we survey recent research work in the design of fault-tolerant three-dimensional (3D) network-on-chip (NoC), which has drawn lots of research attention from both academia and industry. To be specific, we discuss the emerging defects introduced in 3D integration, the state-of-the-art fault-tolerant 3D router designs, various fault-tolerant routing algorithms in three-dimension, as well as the architecture and design methodologies to tolerate defective TSVs in 3D-NoC. Finally, we highlight open challenges and future research directions in this domain.