High Performance Non-blocking Switch Design in 3D Die-Stacking Technology

Abstract

Die stacking is a promising new technology that enables integration of devices in the third dimension. It allows the stacking of multiple active layers directly on top of one another with short, dense die-to-die vias providing communication. Previous work has shown significant bene¿ts at all design targets, from stacking memory on logic to partitioning individual architectural units across multiple layers. Many high-speed processor units—ALUs, register ¿les, caches, and instruction schedulers—have all been designed in 3D, achieving signi¿cant, simultaneous power savings and performance boosts. Other work has looked at the implementation of network-on-chip in a die stack but restricted the focus to planar designs of the various unit(processors, routers, etc.). This work follows up on these two re-search areas to explore the 3D design of router components, speci¿cally the crossbar. We examine the implementation of a crossbar and two multistage interconnect networks to determine the potential bene¿ts of 3D implementations. Compared to equivalent planar designs,we achieve a maximum delay reduction of 26% and maximum power savings of 24%.