Evolution of States in Single Electron Tunneling Circuits

Abstract

This paper presents a numerical solution of the dynamic Master Equation that governs the evolution of states in single electronic systems. The solution presents the ensemble average occupancy of states during the transient stage and at the steady-state. It is shown that the settling time of the circuits resulting from a change in bias conditions depends on the initial and final bias conditions. The asymmetrical settling times must be taken into consideration for the design of digital and analogue single electronic circuits