The capacitance-voltage characteristics of metal-ferroelectric-insulator-silicon structures for non-volatile memory applications

Abstract

The electrical characteristics of metal-ferroelectric-insulalor-silicon (MFIS) structures are studied. The ferroelectric layer is lead-zirconate-titanate (PZr) and the insulator layer is Ta,05. The orientation of the C-V hysteresis loop depends on both the polarization of the ferroelectric layer and the trapped charges injected into the insularor layer. These two effects are opposite to each other. The C-Vorientation is counterclockwise when the applied voltage is below 7 V and clockwise above 7 V The C-V memory window j r s t increases and then decreases with the applied sweep voltage. These phenomena are explained by the polarization and the charge trapping effects.