An SOPC test strategy based on wrapper/TAM co-optimization

Abstract

Recently, system-on-a-Programmable-Chip (SOPC) has become more and more popular. However, prior research only concentrated on System on Chip (SoC) test problem. In this paper, we address the SOPC test problem. An SOPC test strategy has been proposed to solve the wrapper/TAM co-optimization problem for the SOPC. Our wrapper design algorithm is proposed on earlier approach by arranging the internal scan chains scientifically to archive lower testing time. Then we present a new test schedule technique, in which the testing time for each IP cores are calculated by our wrapper design algorithm. Experimental results are present for ITC'02 test benchmark as well as Integrated Processor.