Adaptive Grid Generation for Semiconductor Device Simulation

W. M. Coughran, M. Pinto, R.K. Smith
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引用次数: 3

Abstract

In general the inim grid neecls modification at some biases in order to meet an allowable amount of discretization error. After each nonlinear solve. the grid is adapted - locally refin4umfined - and the solution is recomputed, using the final grid at each condition as an iiiiual estimate for the next. The key ID implementing an robust and efficient scheme is the selection of a proper error indlicator. We have found for instance that the local truncation error (LTE) is extremely poor as it frequently misses the proper regions to refine. Comparison of results on a linearly doped diode before and after refinement using LE and any estimate based on the solution elm (figure 4) show that LTE does not achieve the expected h2 (4X) reduction in error, due to the fact that it is non-’zero only at the ends of the space-charge region and where l for the standard box method, we solve 3x3 linear systems for the coefficients of quadratic basis functions. We note that, since the usual ScharfetterCummel discretization does not quite fit into a Galierkin hierarchy. special cam must be taken with the continuity equations; see 141. The calculations are completely vector/parallel and are a negligible expense. The advantage of BW is illustrated by the Poisson solution to a reverse biased p+n &ode (figure 6). The actual error extends throughout the depletion region, whereas the BW estimate is only large in the vicinity of the junction. However, both lead to a 4X reduction in error after refinement, although the BW estimate adds 25X less gnd points. l?re key observation is that the actual solution error can be influenced in regions not needing refinement by errors made some distance away. Furthmore, the actual error is often extremely expensive to estimate. The remaining CMOS grids (figures 6-8) show selected results ol adaptive refinmentslunrefinements at points in IV continuation simulation [5]. Figure 6 cormponds to the off-state wllae a large potential barrier exists at the tub-substrate junction: refined regions extend upward along the right sidewall and across the trench. Figure 7. a bias point near triggering, has moved the grid to follow the barrier to the epi-subrstmte interface (Kirk effect) and has refined the tubtrench interface due to sharper band bending. Figure 8, a point in the on-state, has completely unrefined dd junctions due to high-level injection, and the resulting carrier plasma butts against the substrate: the large difference in tub potentials sets up a barrier on the right,, including a point of near singularity at the n+ tub contact The average number of gnd points required to trace the IV curve to 5OmV accuracy in poten~tials is ~1700 using full adaption, and the overhead versus knowing the actual grid a priori is about 50%. If a static grid wen to be used, more than 4OOO @d points would have been required, and even then the error indicator would be nect!sq to pply piace them. If the initial grid were always used, the extracted triggeriholding points would have been in mor by as much as 3096.
半导体器件仿真中的自适应网格生成
一般情况下,微网格需要在一定的偏差处进行修正,以满足允许的离散误差。每次非线性求解后。网格被调整——局部细化——并重新计算解决方案,使用每个条件下的最终网格作为下一个条件的初始估计。选择正确的错误指示符是实现稳健高效方案的关键。例如,我们发现局部截断误差(LTE)非常小,因为它经常错过适当的区域来改进。使用LE和基于解elm的任何估计对线性掺杂二极管进行改进前后的结果比较(图4)表明,LTE并没有达到预期的h2 (4X)误差减少,这是由于它仅在空间电荷区域的末端是非零的事实,其中l对于标准盒方法,我们求解3x3线性系统的二次基函数的系数。我们注意到,由于通常的ScharfetterCummel离散化并不完全适合加利尔金层次结构。对于连续性方程必须采用特殊凸轮;看到141。计算完全是矢量/并行的,费用可以忽略不计。BW的优势由反向偏置p+n &ode的泊松解说明(图6)。实际误差扩展到整个耗尽区,而BW估计仅在结附近较大。然而,两者都导致改进后误差减少4倍,尽管BW估计增加了25倍的gnd点。l ?一个关键的观察是,实际的解误差可以在不需要细化的区域受到一定距离外的误差的影响。此外,估计实际误差的成本通常非常高。其余的CMOS网格(图6-8)显示了在IV延拓模拟中各点的自适应细化和非细化所选择的结果[5]。图6与非状态井相对应,在管道-衬底交界处存在一个大的势垒:精炼区域沿着右侧壁向上延伸并穿过沟槽。图7。靠近触发的偏置点,将网格移动到epi-subrstmte界面(Kirk效应),并由于更尖锐的波段弯曲而改进了管槽界面。图8所示,在使用状态,完全未经提炼的dd连接由于高层注入,以及由此产生的载波等离子屁股对衬底:大浴缸差势设置一个障碍在右边,,包括一个点在奇点附近的n +浴缸接触接地的平均数量点跟踪IV曲线5 omv所需精度在poten ~多弧离子镀使用完整的适应,~ 1700的开销和了解实际电网先验约为50%。如果要使用静态网格,则需要超过4,000个@d点,即使如此,错误指示器也会紧随其后!要把它们放好。如果始终使用初始网格,则提取的触发器保持点将增加多达3096个。
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