The memory structures of ATLAS I, a high-performance, 16/spl times/16 ATM switch supporting backpressure

Abstract

We present the overall structure of ATLAS I, emphasizing the memory use and requirements. We categorize these requirements in functionality and bandwidth and present the solutions we used in the first implementation of ATLAS I in a 0.35 /spl mu/ CMOS technology. This implementation can serve as a starting point in the design of future switches with functionality similar to ATLAS I.