Thermal Impacts on NoC Interconnects

Abstract

Thermal issues are an increasing concern in microelectronics due to increased power density as well as the increasing vulnerability of the system to temperature effects (delay, leakage, reliability). NoCs promise to relieve many of the scaling problems that arise with increasing levels of on-chip system integration. This paper addressed the impacts on NoC interconnect circuits under harsh uniform temperature changes and non-uniform spatial temperature distribution profiles. Temporal and spatial thermal variations were addressed in 65 nm, 45 nm and 32 nm interconnect circuits. Standard repeater insertion and differential current sensing techniques have been implemented. The circuits were analyzed in temperatures as high as 150degC for the temporal variations, with a maximum temperature difference through wire of up to 50degC. High temperature caused more delay and power overhead in smaller technologies, i.e. 45 nm and 32 nm, by as much as 71% at 150degC for a given wirelength of 3 mm in 32 nm. Spatial temperature distribution profile influenced the propagation delay by 14.7% for a maximum thermal gradient of 50degC in the worst case for a 32 nm, 3 mm repeated wire. However, the delay degradation of an alternative differential current sensing (DCS) technique is largely determined by the amplifier temperature. Future work may consider the modeling of self-heating of the interconnect circuits