Characteristics of submicrometer LOCOS isolation

Abstract

For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined.