B. Nodari, L. Caponetto, G. Galbit, S. Viret, S. Scarfi
{"title":"A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC","authors":"B. Nodari, L. Caponetto, G. Galbit, S. Viret, S. Scarfi","doi":"10.22323/1.343.0099","DOIUrl":null,"url":null,"abstract":"The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) andStrip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the HighLuminosity LHC (HL-LHC). It collects the digital data coming from eight upstream front-endchips (either MPAs or CBCs, depending on the module type), formats the signal in data packetscontaining the trigger information from eight bunch crossings and the raw data from eventspassing the first trigger level, and finally transmits them to the LpGBT unit. The design and itsimplementation in a 65 nm CMOS technology of the first prototype that integrates allfunctionalities for system level operation are presented in this contribution.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.22323/1.343.0099","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) andStrip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the HighLuminosity LHC (HL-LHC). It collects the digital data coming from eight upstream front-endchips (either MPAs or CBCs, depending on the module type), formats the signal in data packetscontaining the trigger information from eight bunch crossings and the raw data from eventspassing the first trigger level, and finally transmits them to the LpGBT unit. The design and itsimplementation in a 65 nm CMOS technology of the first prototype that integrates allfunctionalities for system level operation are presented in this contribution.