Dynamic Fault Imaging of VLSI Random Logic Devices

Abstract

A technique is described for acquiring and imaging faults in random logic devices such as microprocessors and other VLSI chips. Logic states for both faulty and fault-free devices are imaged separately by means of stroboscopic voltage contrast in a scanning electron microscope and are then stored as incremental time sequences of images. These sequences represent the time evolution of states during a particular device test and are then compared in an image array processor. The divergences or changes between the faulty and fault-free device evolutions represent faults, which are then displayed on a color monitor. The architecture and implementation of the Dynamic Fault Imager is described. Several examples using highly-integrated microprocessors are given, including the imaging of functional failures, voltage marginalities, and critical speed path mapping. A partial classification of faults is presented, as well as a discussion of future trends. The technique appears to have wide application to solving problems in the design and manufacturing of future VLSI devices.