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Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology

International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI:10.1007/978-981-32-9767-8_11
S. Siddamal, Suhas B. Shirol, Shraddha B Hiremath, N. Iyer
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引用次数: 3
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基于0.18µm CMOS技术的混合信号经过时间计数器的设计与物理实现
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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International Symposium on VLSI Design and Test
International Symposium on VLSI Design and Test
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