Fabrication of high-performance InP MESFETs with in-situ pulse-plated metal gates

S. Uno, T. Hashizume, T. Sato, H. Hasegawa
{"title":"Fabrication of high-performance InP MESFETs with in-situ pulse-plated metal gates","authors":"S. Uno, T. Hashizume, T. Sato, H. Hasegawa","doi":"10.1109/ICIPRM.1996.492048","DOIUrl":null,"url":null,"abstract":"Although InP has higher saturation velocity and higher thermal conductivity than GaAs, its use in the active channel of electron devices has been limited by lack of suitable Schottky gate technology. The purpose of this paper is to demonstrate that high-performance InP MESFETs with Schottky barrier heights (SBHs)=0.85-0.89 eV can be realized by a novel in-situ electrochemical etching/plating technique. The InP Schottky barriers produced by this electrochemical process are free of interfacial oxides and Fermi level pinning is removed, realizing workfunction-dependent SBHs. High-barrier height, low-leakage and stable InP MESFETs are realized for the first time using this process.","PeriodicalId":268278,"journal":{"name":"Proceedings of 8th International Conference on Indium Phosphide and Related Materials","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 8th International Conference on Indium Phosphide and Related Materials","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIPRM.1996.492048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Although InP has higher saturation velocity and higher thermal conductivity than GaAs, its use in the active channel of electron devices has been limited by lack of suitable Schottky gate technology. The purpose of this paper is to demonstrate that high-performance InP MESFETs with Schottky barrier heights (SBHs)=0.85-0.89 eV can be realized by a novel in-situ electrochemical etching/plating technique. The InP Schottky barriers produced by this electrochemical process are free of interfacial oxides and Fermi level pinning is removed, realizing workfunction-dependent SBHs. High-barrier height, low-leakage and stable InP MESFETs are realized for the first time using this process.
原位脉冲镀金属栅极制备高性能InP mesfet
尽管InP具有比GaAs更高的饱和速度和更高的热导率,但由于缺乏合适的肖特基栅技术,其在电子器件有源通道中的应用受到限制。本文的目的是证明一种新的原位电化学蚀刻/电镀技术可以实现肖特基势垒高度(SBHs)=0.85-0.89 eV的高性能InP mesfet。这种电化学过程产生的InP肖特基势垒不含界面氧化物,消除了费米能级钉住,实现了依赖于工作功能的SBHs。利用该工艺首次实现了高势垒高度、低泄漏和稳定的InP mesfet。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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