A VCO phase noise reduction technique to suppress the active device contribution

Kai Men, Bharatha Kumar Thangarasu, K. Yeo
{"title":"A VCO phase noise reduction technique to suppress the active device contribution","authors":"Kai Men, Bharatha Kumar Thangarasu, K. Yeo","doi":"10.1109/INEC.2016.7589433","DOIUrl":null,"url":null,"abstract":"In this paper, a voltage-controlled oscillator (VCO) phase noise improvement technique is proposed that suppresses the phase noise contribution from the active devices. The cyclostationary noise at the VCO tail bias current source, which exhibits twice of the operation frequency, is utilized to switch the biasing transistor on and off periodically. The dc power consumption of the proposed VCO designed in 0.18 μm SiGe process is 1.03 mW with a supply voltage of 1.8 V. The simulated phase noise is -120.0 dBc/Hz at 1 MHz offset frequency and the figure-of-merit (FoM) is 179.8 dBc/Hz.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"72 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2016.7589433","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

In this paper, a voltage-controlled oscillator (VCO) phase noise improvement technique is proposed that suppresses the phase noise contribution from the active devices. The cyclostationary noise at the VCO tail bias current source, which exhibits twice of the operation frequency, is utilized to switch the biasing transistor on and off periodically. The dc power consumption of the proposed VCO designed in 0.18 μm SiGe process is 1.03 mW with a supply voltage of 1.8 V. The simulated phase noise is -120.0 dBc/Hz at 1 MHz offset frequency and the figure-of-merit (FoM) is 179.8 dBc/Hz.
一种抑制有源器件贡献的压控振荡器相位降噪技术
本文提出了一种抑制有源器件相位噪声贡献的压控振荡器(VCO)相位噪声改善技术。利用压控振荡器尾部偏置电流源处两倍于工作频率的周期平稳噪声周期性地开关偏置晶体管。采用0.18 μm SiGe工艺设计的压控振荡器在1.8 V电源电压下的直流功耗为1.03 mW。在1mhz偏置频率下,仿真相位噪声为-120.0 dBc/Hz,性能因数(FoM)为179.8 dBc/Hz。
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