Test time reduction for I/sub DDQ/ testing by arranging test vectors

Abstract

In this paper, test time reduction for I/sub DDQ/ testing is discussed. Although I/sub DDQ/ testing is known to be effective in detecting faults in CMOS circuits, the test time of I/sub DDQ/ testing is larger than that of logic testing. It is shown that the test time of I/sub DDQ/ test mostly depends on the switching current. To reduce the test time of I/sub DDQ/ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.