Design and Analysis of Power Integrity of DDR5 Dual In-Line Memory Modules

Abstract

In today’s high speed design space, speed is the main factor determining the performance of the product. Dual In-line memory modules (DIMM) designs for DDR5 are packed with many high-speed DRAMs with signal speeds high enough that stack-up of the printed circuit board (PCB) play a critical role in the overall DIMM performance. At speeds of 6400 Mbps, power integrity becomes as important as signal integrity. On a first order approximation, power integrity basically involves PCB stack-up and decoupling capacitors design. This paper covers significance of power distribution network (PDN) symmetry in a symmetric stack-up for two-sided component mounted PCBs like DIMM modules running at multi-Gbps speeds.