Customized wafer level verification methodology: quality risk pre-diagnosis with enhanced screen-ability of stand-by stress-related deteriorations

Abstract

This paper presents an accelerated stress of product at the wafer level for quality evaluations by performing pre-assessment of stand-by stress-related deteriorations. It is a customized defect-inducing evaluation methodology designed to have consistency with longer term package level test. The test was conducted on 18-nm 8Gb DDR4 DRAM wafers under various time and voltage stress conditions at elevated temperature to find the optimal condition for quality monitoring purpose. Then, the screen-ability was empirically verified through physical failure analysis and statistically verified through Fisher's Exact Test.