Hardware implementation of boosting based object detection using a high level description

Abstract

The face detection is a fundamental prerequisite step in the process of face recognition. The focus of this paper is the implementation of a real time embedded face detection system while relying on high level description language such as SystemC. Recently, the boosting based object detection algorithms proposed by have gained a lot of attention and are considered as the fastest accurate object detection algorithms today. However, the embedded implementation of such algorithms into hardware is still a challenge, since these algorithms are heavily based on memory access. We built a parallel implementation that exploits the parallelism and the pipelining in these algorithms. We show that, using a SystemC description model paired with a mainstream automatic synthesis tool, can lead to an efficient hardware implementation. We also display some of the tradeoffs and considerations, for this implementation to be effective. This implementation proves capable of increasing the speed of the detector as well as bringing regularity in time consuming. The design implementation is reasonably low on FPGA resource utilization.