The double exposure strategy using OPC and simulation and the performance on wafer with sub-0.10 /spl mu/m design rule in ArF lithography

Abstract

Lately, photolithography is seen as the bottleneck to sub-0.1 /spl mu/m patterning. Namely, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as in the cell region into the resolution limit of exposure tools. Although it is common to use single exposure for lithographic layer formation, an ArF double exposure technique (DET) strategy, based on manual OPC and an in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method for overcoming the limit and its results on wafer are shown. The in-house simulation tool used in this paper can predict the wafer pattern and process margin of a lithographic layer and shows good validity in the ArF process.