Experiments and 2D-simulations for quasi-saturation effect in ponver VDMOS transistors

Abstract

Quasi-saturation phenomena in power VDMOS transistors have been studied extensively by experiments and also by two dimensional device simulation. It has been found that the quasi-saturation current is proportional to the effective cell-to-cell spacing, and beyond the critical point, carrier drift velocity in JFET region is saturated and carrier modulation occurs under the gate region. The results of this work shows that a power VDMOS transistor should be designed to keep the operating current smaller than one half of the critical current (I*) rather than I* reported previously. This is obtained from the detailed analysis of the severe non-linearity of the on-resistance due to mobility degradation as well as to the channel length modulation in the JFET region.