Power dissipation at MOSFET gate port of class D RF power amplifier

TENCON 2010 - 2010 IEEE Region 10 Conference Pub Date : 2010-11-01 DOI:10.1109/TENCON.2010.5686117

Takuya Kudo, Toru Umeki, A. Kiri, T. Suetsugu

引用次数: 0

Abstract

In this paper, gate port power dissipation of class D amplifier is obtained as a function of amplitude and offset of drive signal with Pspice simulation. It is found that the amplitude of gate signal should be higher than 4 V in order to keep 80% efficiency in power stage of class D amplifier

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D类射频功率放大器MOSFET栅极端口的功耗

本文通过Pspice仿真得到了D类放大器的栅极功耗与驱动信号的幅值和偏置的函数关系。研究发现，要使D类放大器的功率级保持80%的效率，栅极信号的幅值应高于4 V

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

TENCON 2010 - 2010 IEEE Region 10 Conference

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