Characterization and modeling of simultaneously fabricated DMOS and VMOS transistors

Abstract

A process has been designed which allows the simultaneous fabrication of V-groove MOS (VMOS) and double-diffused MOS (DMOS) transistors. The main objective of this work was to characterize and compare the physical and electrical properties of the two MOS devices. Physical parameters of the VMOS transistors were extracted from their vertical impurity profile measured by spreading resistance. The measured channel lengths and peak impurity concentrations were correlated with the gain factor and threshold voltage for several fabrication schedules. Properties of the lateral impurity profile were inferred from a comparison of the electrical characteristics of the VMOS and DMOS devices. In order to accurately model device performance in the saturated region, a one-dimensional solution of Poisson's equation was derived for the region surrounding the channel-substrate junction.