V. Trivedi, J. John, J. Young, T. Dao, D. Morgan, I. To, R. Ma, D. Hammock, S. Mehrotra, L. Radic, B. Grote, T. Roggenbauer, J. Kirchgessner
{"title":"A 90nm BiCMOS technology featuring 400GHz fMAX SiGe:C HBT","authors":"V. Trivedi, J. John, J. Young, T. Dao, D. Morgan, I. To, R. Ma, D. Hammock, S. Mehrotra, L. Radic, B. Grote, T. Roggenbauer, J. Kirchgessner","doi":"10.1109/BCTM.2016.7738951","DOIUrl":null,"url":null,"abstract":"A 90nm BiCMOS technology with a SiGe:C HBT having fMAX >400GHz is presented. Both lateral and vertical scaling of the SiGe bipolar transistor are described, enabling SiGe HBT performance metrics fT/fMAX of ~230GHz/400GHz to be achieved with a minimum gate delay of <;3ps. A medium breakdown device is also integrated, achieving an fT*BVCEO product of 310GHz*V. CMOS implant and HBT process optimizations to address the additional thermal budget of the HBT module are also discussed. In concert with high-quality passives, this technology is especially suited for millimeter wave applications with high digital gate density requirements.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2016.7738951","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
A 90nm BiCMOS technology with a SiGe:C HBT having fMAX >400GHz is presented. Both lateral and vertical scaling of the SiGe bipolar transistor are described, enabling SiGe HBT performance metrics fT/fMAX of ~230GHz/400GHz to be achieved with a minimum gate delay of <;3ps. A medium breakdown device is also integrated, achieving an fT*BVCEO product of 310GHz*V. CMOS implant and HBT process optimizations to address the additional thermal budget of the HBT module are also discussed. In concert with high-quality passives, this technology is especially suited for millimeter wave applications with high digital gate density requirements.