Transparent SOC: on-chip analyzing techniques and implementation for embedded processor

Abstract

An on-chip analysis technique for SOC, which enables system performance to be improved, was developed. The key to this technique is the synchronized analysis of the whole SOC. This is made possible by a circuit structure in which small circuits for analysis are distributed at points on the SOC to be analyzed, and these circuits operate in synchronization through a special network. Benchmarks for multimedia operations (including MPEG encoding) show that this analysis enables us to improve system performance by 17% with minimum trial-and-error. In addition, it was confirmed that the negative impact on chip area when applying this technique is very small. And it is concluded that SOC design time can be shortened during the system-development stage by using this technique.